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MC74HC4538A Dual Precision Monostable Multivibrator (Retriggerable, Resettable)
The MC74HC4538A is identical in pinout to the MC14538B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This dual monostable multivibrator may be triggered by either the positive or the negative edge of an input pulse, and produces a precision output pulse over a wide range of pulse widths. Because the device has conditioned trigger inputs, there are no trigger-input rise and fall time restrictions. The output pulse width is determined by the external timing components, Rx and Cx. The device has a reset function which forces the Q output low and the Q output high, regardless of the state of the output pulse circuitry.
Features http://onsemi.com MARKING DIAGRAMS
16 16 1 PDIP-16 N SUFFIX CASE 648 MC74HC4538AN AWLYYWWG 1 16 16 1 SOIC-16 D SUFFIX CASE 751B 1 16 16 1 TSSOP-16 DT SUFFIX CASE 948F 1 16 16 1 SOEIAJ-16 F SUFFIX CASE 966 1 74HC4538A ALYWG HC45 38A ALYWG G HC4538AG AWLYWW
* Unlimited Rise and Fall Times Allowed on the Trigger Inputs * Output Pulse is Independent of the Trigger Pulse Width * 10% Guaranteed Pulse Width Variation from Part to Part * * * * * * * *
(Using the Same Test Jig) Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 3.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 145 FETs or 36 Equivalent Gates Pb-Free Packages are Available*
A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb-Free Package G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
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June, 2005 - Rev. 9
Publication Order Number: MC74HC4538A/D
MC74HC4538A
GND CX1/RX1 RESET 1 A1 B1 Q1 Q1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC GND CX2/RX2 RESET 2 A2 B2 Q2 Q2 Reset H H H H H H L
FUNCTION TABLE
Inputs A L X H L,H, L X X L X H L,H, X X Not Triggered Not Triggered Not Triggered Not Triggered L H Not Triggered B H Outputs Q Q
Figure 1. Pin Assignment
CX1 RX1 VCC 1 TRIGGER INPUTS A1 B1 4 5 2 6 7 Q1 Q1
PIN 16 = VCC PIN 8 = GND RX AND CX ARE EXTERNAL COMPONENTS PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND
RESET 1
3 CX2 RX2 VCC 15 14 TRIGGER INPUTS A2 B2 12 11 10 9 Q2 Q2
RESET 2
13
Figure 2. Logic Diagram
ORDERING INFORMATION
Device MC74HC4538AN MC74HC4538ANG MC74HC4538AD MC74HC4538ADG MC74HC4538ADR2 MC74HC4538ADR2G MC74HC4538ADTR2 MC74HC4538ADTR2G MC74HC4538AF MC74HC4538AFG MC74HC4538AFEL MC74HC4538AFELG Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* TSSOP-16* SOEIAJ-16 SOEIAJ-16 (Pb-Free) SOEIAJ-16 SOEIAJ-16 (Pb-Free) Shipping 500 Units / Box 500 Units / Box 48 Units / Rail 48 Units / Rail 2500 Units / Reel 2500 Units / Reel 2500 Units / Reel 2500 Units / Reel 50 Units / Rail 50 Units / Rail 2000 Units / Reel 2000 Units / Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74HC4538A
MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG TL TJ qJA DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead temperature, 1 mm from Case for 10 Seconds Junction temperature under Bias Thermal resistance PDIP SOIC TSSOP PDIP SOIC TSSOP (Note 1) A, B, Reset CX, RX Parameter Value *0.5 to )7.0 *0.5 v VI v VCC )0.5 *0.5 v VO v VCC )0.5 $20 $30 $25 $25 $100 $100 *65 to )150 260 )150 78 112 148 750 500 450 Level 1 Oxygen Index: 30% - 35% Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 85_C (Note 5) UL-94-VO (0.125 in) >2000 >100 >500 $300 V Unit V V V mA mA mA mA mA _C _C _C _C/W
PD
Power Dissipation in Still Air at 85_C
mW
MSL FR VESD
Moisture Sensitivity Flammability Rating ESD Withstand Voltage
ILatchup
Latchup Performance
mA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78. 6. For high frequency or heavy load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 7) A or B (Figure 5) Rx Cx External Timing Resistor External Timing Capacitor VCC < 4.5 V VCC 4.5 V VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min 3.0* 0 -55 0 0 0 - 1.0 2.0 0 Max 6.0 VCC +125 1000 500 400 No Limit Unit V V _C ns
kW mF
*The HC4538A will function at 2.0 V but for optimum pulse-width stability, VCC should be above 3.0 V. The maximum allowable values of Rx and Cx are a function of the leakage of capacitor Cx, the leakage of the HC4538A, and leakage due to board layout and surface resistance. For most applications, Cx/Rx should be limited to a maximum value of 10 mF/1.0 MW. Values of Cx > 1.0 mF may cause a problem during power down (see Power Down Considerations). Susceptibility to externally induced noise signals may occur for Rx > 1.0 MW. 7. Unused inputs may not be left open. All inputs must be tied to a high-logic voltage level or a low-logic input voltage level. 8. Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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DC CHARACTERISTICS
Symbol ICC VOH VOL VIH ICC VIL Iin Iin Maximum Supply Current (per package) Active State Maximum Quiescent Supply Current (per package) Standby State Maximum Input Leakage Current (Rx, Cx) Maximum Input Leakage Current (A, B, Reset) Maximum Low-Level Output Voltage Minimum High-Level Output Voltage Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter Vin = VCC or GND Q1 and Q2 = High Iout = 0 mA Pins 2 and 14 = 0.5 VCC Vin = VCC or GND Q1 and Q2 = Low Iout = 0 mA Vin = VCC or GND Vin = VCC or GND Vin = VIH or VIL |Iout| v 4.0 mA |Iout| v 5.2 mA Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL |Iout| v - 4.0 mA |Iout| v - 5.2 mA Vin = VIH or VIL |Iout| v 20 mA Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA Test Conditions
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MC74HC4538A
4 VCC V 6.0 6.0 6.0 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 1.5 3.15 4.2 3.98 5.48 -55 to 25_C Min 1.9 4.4 5.9 25_C 0.1 0.26 0.26 0.5 1.35 1.8 Max 50 400 130 0.1 0.1 0.1 Guaranteed Limits 1.5 3.15 4.2 3.84 5.34 Min 1.9 4.4 5.9 -45_C to 85_C v 85_C 500 1.0 0.33 0.33 0.5 1.35 1.8 Max 600 220 0.1 0.1 0.1 1.5 3.15 4.2 Min 3.7 5.2 1.9 4.4 5.9 v 125_C -55_C to 125_C 500 1.0 Max 0.5 1.35 1.8 800 350 0.4 0.4 0.1 0.1 0.1 Unit mA mA mA V V V V nA
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*Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
TIMING CHARACTERISTICS (Input tr = tf = 6.0 ns)
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Symbol
CPD
tTLH, tTHL
tPLH
tPHL
tPHL
tPLH
tr, tf
trec
Cin
tw
tw
Power Dissipation Capacitance (per Multivibrator)*
A or B (Figure 7)
Maximum Input Rise and Fall Times, Reset (Figure 7)
Minimum Pulse Width, Reset (Figure 7)
Minimum Pulse Width, Input A or B (Figure 6)
Minimum Recovery Time, Inactive to A or B (Figure 7)
Maximum Input Capacitance
Maximum Output Transition Time, Any Output (Figures 7 and 8)
Maximum Propagation Delay Reset to NQ (Figures 7 and 8)
Maximum Propagation Delay Reset to Q (Figures 7 and 8)
Maximum Propagation Delay Input A or B to NQ (Figures 6 and 8)
Maximum Propagation Delay Input A or B to Q (Figures 6 and 8)
Parameter
Parameter
(A. B, Reset) (Cx, Rx)
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MC74HC4538A
5 VCC V VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - -55 to 25_C -55 to 25_C Min Min 60 12 10 60 12 10 0 0 0 Typical @ 25C, VCC = 5.0 V 1000 500 400 Max Max 175 35 30 175 35 30 195 39 33 175 35 30 10 25 75 15 13 Guaranteed Limits Guaranteed Limits Min 150 Min 75 15 13 75 15 13 0 0 0 No Limit v 85_C v 85_C 1000 500 400 Max Max 220 44 37 220 44 37 245 49 42 220 44 37 10 25 95 19 16 Min Min 90 18 15 90 18 15 0 0 0 v 125_C v 125_C 1000 500 400 Max Max 110 22 19 265 53 45 265 53 45 295 59 50 265 53 45 10 25 Unit Unit pF pF ns ns ns ns ns ns ns ns ns
MC74HC4538A
k, OUTPUT PULSE WIDTH CONSTANT (TYPICAL)
0.7
OUTPUT PULSE WIDTH ()
OUTPUT PULSE WIDTH () (NORMALIZED TO 5 V NUMBER)
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OUTPUT PULSE WIDTH CHARACTERISTICS (CL = 50 pF)t
Conditions Guaranteed Limits v 85_C Symbol Parameter Timing Components VCC V -55 to 25_C Min v 125_C Max Min 0.6 Max 0.8 Min Max Unit ms % % Output Pulse Width* (Figures 6 and 8) 5.0 0.63 Rx = 10 kW, Cx = 0.1 mFIII - - - - 0.77 0.59 0.81 - - Pulse Width Match Between Circuits in the same Package Pulse Width Match Variation (Part to Part) 5.0 10 *For output pulse widths greater than 100 ms, typically = kRxCx, where the value of k may be found in Figure 3. 0.8 TA = 25C 10 s 1s 100 ms 10 ms 1 ms 100 ms 10 ms 1 ms 1 MW 100 kW 10 kW 0.01 0.1 1 10 100 VCC = 5 V, TA = 25C 0.6 0.5 0.4 0.3 1 2 3 4 5 6 7 1 kW 100 ns 0.00001 0.0001 0.001 VCC, POWER SUPPLY VOLTAGE (VOLTS) CAPACITANCE (mF)
Figure 3. Typical Output Pulse Width Constant, k, versus Supply Voltage (For output pulse widths > 100 ms: = kRxCx)
Figure 4. Output Pulse Width versus Timing Capacitance
1.1 1 0.9 0.8 0.7 0.6 0.5 Rx = 1 MW Cx = 0.1 mF Rx = 100 kW Cx = 1000 pF TA = 25C
1
2 3 4 5 6 VCC, POWER SUPPLY VOLTAGE (VOLTS)
7
Figure 5. Normalized Output Pulse Width versus Power Supply Voltage
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MC74HC4538A
1.1 OUTPUT PULSE WIDTH () (NORMALIZED TO 25_C NUMBER) 1.05 1 VCC = 6 V 0.95 0.9 0.85 VCC = 3 V 0.8 -75 -50 -25 0 25 50 75 100 125 150 Rx = 10 kW Cx = 0.1 mF
TA, AMBIENT TEMPERATURE (C)
Figure 6. Normalized Output Pulse Width versus Power Supply Voltage
1.03 1.02 1.01 1 0.99 0.98 0.97 -75 -50 VCC = 5.5 V VCC = 5 V VCC = 4.5 V -25 0 25 50 75 100 125 150 Rx = 10 kW Cx = 0.1 mF
OUTPUT PULSE WIDTH () (NORMALIZED TO 25_C NUMBER)
TA, AMBIENT TEMPERATURE (C)
Figure 7. Normalized Output Pulse Width versus Power Supply Voltage
tw(H) VCC 50% A tw(L) B 50% GND tPLH 50% Q tPHL Q 50% tPHL tPLH VCC GND
Figure 8. Switching Waveform http://onsemi.com
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MC74HC4538A
tr 90% 10% trr VCC 50% B tf 50% tTLH 90% Q tTHL Q 90% 10% 10% tPLH 50% tw(L) tPHL 50% 50% tf 90% 10% trec + trr (RETRIGGERED PULSE) VCC GND GND tf VCC GND
A
RESET
Figure 9. Switching Waveform
TEST POINT OUTPUT DEVICE UNDER TEST CL*
*Includes all probe and jig capacitance
Figure 10. Test Circuit
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MC74HC4538A
PIN DESCRIPTIONS
INPUTS A1, A2 (Pins 4, 12)
Positive-edge trigger inputs. A rising-edge signal on either of these pins triggers the corresponding multivibrator when there is a high level on the B1 or B2 input.
B1, B2 (Pins 5, 11)
capacitors (see the Block Diagram). Polystyrene capacitors are recommended for optimum pulse width control. Electrolytic capacitors are not recommended due to high leakages associated with these type capacitors.
GND (Pins 1 and 15)
Negative-edge trigger inputs. A falling-edge signal on either of these pins triggers the corresponding multivibrator when there is a low level on the A1 or A2 input.
Reset 1, Reset 2 (Pins 3, 13)
External ground. The external timing capacitors discharge to ground through these pins.
OUTPUTS Q1, Q2 (Pins 6, 10)
Reset inputs (active low). When a low level is applied to one of these pins, the Q output of the corresponding multivibrator is reset to a low level and the Q output is set to a high level.
CX1/RX1 and CX2/RX2 (Pins 2 and 14)
Noninverted monostable outputs. These pins (normally low) pulse high when the multivibrator is triggered at either the A or the B input. The width of the pulse is determined by the external timing components, RX and CX.
Q1, Q2 (Pins 7, 9)
External timing components. These pins are tied to the common points of the external timing resistors and
RxCx UPPER REFERENCE CIRCUIT - + Vre, UPPER LOWER REFERENCE CIRCUIT - +
Inverted monostable outputs. These pins (normally high) pulse low when the multivibrator is triggered at either the A or the B input. These outputs are the inverse of Q1 and Q2.
OUTPUT LATCH
VCC
VCC
M1 2 kW
M2 M3
Vre, LOWER
Q
Q
TRIGGER CONTROL CIRCUIT A C CB R Q TRIGGER CONTROL RESET CIRCUIT
B
RESET
POWER ON RESET RESET LATCH
Figure 11. Logic Detail (1/2 the Device) http://onsemi.com
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MC74HC4538A
CIRCUIT OPERATION Figure 12 shows the HC4538A configured in the retriggerable mode. Briefly, the device operates as follows (refer to Figure 10): In the quiescent state, the external timing capacitor, Cx, is charged to V CC. When a trigger occurs, the Q output goes high and Cx discharges quickly to the lower reference voltage (Vref Lower [ 1/3 V CC). Cx then charges, through Rx, back up to the upper reference voltage (Vref Upper [ 2/3 V CC), at which point the one-shot has timed out and the Q output goes low. The following, more detailed description of the circuit operation refers to both the logic detail (Figure 9) and the timing diagram (Figure 10).
QUIESCENT STATE TRIGGER OPERATION
In the quiescent state, before an input trigger appears, the output latch is high and the reset latch is high (#1 in Figure 10). Thus the Q output (pin 6 or 10) of the monostable multivibrator is low (#2, Figure 10). The output of the trigger-control circuit is low (#3), and transistors M1, M2, and M3 are turned off. The external timing capacitor, Cx, is charged to VCC (#4), and both the upper and lower reference circuit has a low output (#5). In addition, the output of the trigger-control reset circuit is low.
QUIESCENT STATE TRIGGER CYCLE (A INPUT)
The HC4538A is triggered by either a rising-edge signal at input A (#7) or a falling-edge signal at input B (#8), with the unused trigger input and the Reset input held at the voltage levels shown in the Function Table. Either trigger signal will cause the output of the trigger-control circuit to go high (#9). The trigger-control circuit going high simultaneously initiates two events. First, the output latch goes low, thus taking the Q output of the HC4538A to a high state (#10). Second, transistor M3 is turned on, which allows the external timing capacitor, Cx, to rapidly discharge toward ground (#11). (Note that the voltage across Cx appears at the input of both the upper and lower reference circuit comparator). When Cx discharges to the reference voltage of the lower reference circuit (#12), the outputs of both reference circuits will be high (#13). The trigger-control reset circuit goes high, resetting the trigger-control circuit flip-flop to a low state (#14). This turns transistor M3 off again, allowing Cx to begin to charge back up toward VCC, with a time constant t = RxCx (#15). Once the voltage across Cx charges to above the lower reference voltage, the lower reference circuit will go low allowing the monostable multivibrator to be retriggered.
TRIGGER CYCLE (B INPUT) RESET trr RETRIGGER
7
TRIGGER INPUT A (PIN 4 OR 12) TRIGGER INPUT B (PIN 5 OR 11)
9
8 24 14 11 12 13 18 13 6 16 21 23
TRIGGER-CONTROL CIRCUIT OUTPUT RX/CX INPUT (PIN 2 OR 14)
3 4
15
17
Vref LOWER UPPER REFERENCE CIRCUIT LOWER REFERENCE CIRCUIT RESET INPUT (PIN 3 OR 13)
1 5
Vref UPPER
25
20
RESET LATCH
10
22
Q OUTPUT (PIN 6 OR 10)
2
19
+ trr
Figure 12. Timing Diagram
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MC74HC4538A
When Cx charges up to the reference voltage of the upper reference circuit (#17), the output of the upper reference circuit goes low (#18). This causes the output latch to toggle, taking the Q output of the HC4538A to a low state (#19), and completing the time-out cycle.
POWER-DOWN CONSIDERATIONS
Large values of Cx may cause problems when powering down the HC4538A because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor may discharge from VCC through the input protection diodes at pin 2 or pin 14. Current through the protection diodes must be limited to 30 mA; therefore, the turn-off time of the VCC power supply must not be faster than t = VCCCx /(30 mA). For example, if VCC = 5.0 V and Cx = 15 mF, the VCC supply must turn off no faster than t = (5.0 V)(15 mF)/30 mA = 2.5 ms. This is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of VCC to zero volts occurs, the HC4538A may sustain damage. To avoid this possibility, use an external damping diode, Dx, connected as shown in Figure 11. Best results can be achieved if diode Dx is chosen to be a germanium or Schottky type diode able to withstand large current surges.
RESET AND POWER ON RESET OPERATION
occurs, the output of the reset latch goes low (#22), turning on transistor M1. Thus Cx is allowed to quickly charge up to VCC (#23) to await the next trigger signal. On power up of the HC4538A the power-on reset circuit will be high causing a reset condition. This will prevent the trigger-control circuit from accepting a trigger input during this state. The HC4538A's Q outputs are low and the Q not outputs are high.
RETRIGGER OPERATION
A low voltage applied to the Reset pin always forces the Q output of the HC4538A to a low state. The timing diagram illustrates the case in which reset occurs (#20) while Cx is charging up toward the reference voltage of the upper reference circuit (#21). When a reset
When used in the retriggerable mode (Figure 12), the HC4538A may be retriggered during timing out of the output pulse at any time after the trigger-control circuit flip-flop has been reset (#24), and the voltage across Cx is above the lower reference voltage. As long as the Cx voltage is below the lower reference voltage, the reset of the flip-flop is high, disabling any trigger pulse. This prevents M3 from turning on during this period resulting in an output pulse width that is predictable. The amount of undershoot voltage on RxCx during the trigger mode is a function of loop delay, M3 conductivity, and V DD. Minimum retrigger time, trr (Figure 7), is a function of 1) time to discharge R x Cx from V DD to lower reference voltage (T discharge); 2) loop delay (T delay); 3) time to charge Rx Cx from the undershoot voltage back to the lower reference voltage (Tcharge). Figure 13 shows the device configured in the non-retriggerable mode. For additional information, please see Application Note (AN1558/D) titled Characterization of Retrigger Time in the HC4538A Dual Precision Monostable Multivibrator.
DX CX RX VCC
A B
Q Q
RESET
Figure 13. Discharge Protection During Power Down
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MC74HC4538A
TYPICAL APPLICATIONS
CX RISING-EDGE TRIGGER RX VCC Q Q RISING-EDGE TRIGGER CX RX VCC Q Q
A B B = VCC RESET = VCC
A B
RESET = VCC
CX
RX VCC Q FALLING-EDGE TRIGGER
CX
RX VCC Q
A = GND
A B Q
B FALLING-EDGE TRIGGER RESET = VCC
Q
RESET = VCC
Figure 14. Retriggerable Monostable Circuitry
Figure 15. Non-retriggerable Monostable Circuitry
GND A = GND
N/C RXCX Q
VCC
N/C N/C
B Q RESET
Figure 16. Connection of Unused Section
ONE-SHOT SELECTION GUIDE
100 ns MC14528B MC14536B MC14538B MC14541B HC4538A* 1 ms 10 ms 100 ms 1 ms 10 ms 100 ms 1 s 10 s 23 HR 5 MIN *Limited operating voltage (2 -6 V) TOTAL OUTPUT PULSE WIDTH RANGE RECOMMENDED PULSE WIDTH RANGE
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MC74HC4538A
PACKAGE DIMENSIONS
PDIP-16 N SUFFIX CASE 648-08 ISSUE T
-A-
16 9
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC74HC4538A
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE A
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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CCC EEE CCC EEE CCC
K1
SECTION N-N
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC74HC4538A
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX CASE 966-01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74HC4538A
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MC74HC4538A/D

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